The present disclosure relates to controlling clock signals within integrated circuit devices, and more specifically to an improved circuit where activity in a local combinatorial logic structure causes a local resistive voltage to drop below a threshold voltage, causing a comparator to output a clock signal without requiring a clock distribution tree.
Conventional high power chips use 30%-50% of total power consumption just distributing the clock signal. Current solutions use control signals (data valid signals) to perform clock gating. These valid signals and clock gates need to be designed (which consumes resources) and such circuits also consume power.